Cadence Names Top Ten CDNLive India 2017 Best Presentation Award Recipients

Bangalore, India, September 11, 2017 — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the top ten Best Presentation Award winners based on presentations delivered during CDNLive India 2017, the company’s 13th annual flagship user conference. One award recipient was chosen in each of the event’s ten session tracks. The presentations were judged by an expert committee comprised of seasoned professionals from both Cadence and its customer base. The criteria for judging the presentations included originality, relevance to the design community, Cadence® technology use and presentation.

The 2017 Best Presentation Awards in each CDNLive track are as follows:

Track Title Company
System to Signoff: Digital Implementation Achieving “Sustainable” Performance (w/GHz) on Arm Core Using Advanced Methodologies and Cadence Tool MediaTek
System to Signoff: Digital Front-End Design Low Cost High Performance Built-In Self-Test Solution Using Cadence LBIST for Safety Critical SoCs Texas Instruments
System to Signoff: Signoff and Power Analysis Timing Optimization for a Better Signoff Microsemi
Custom and Analog Design: Implementation Implementation of a pCell Feature Above the pCell Hierarchy Using ’Add-On pCell’ in SKILL, Virtuoso Solutions NXP
Custom and Analog Design: Verification Simulator Agnostic Techniques and AMS-XPS-MS Simulator for Faster System-Level AMS Co-Simulation Texas Instruments
System Verification: Advanced Verification Methodology Verification of Multi-Core Sub-System Using Perspec With Re-Usable Stimulus Qualcomm
System Verification: Performance and Debug FuSa DV: Looking for Holes in an ASIL ‘D’ Safety Concept Analog Devices
System Verification: Advanced Verification Methodology Combining UVM-Based Acceleration with In-Circuit Emulation for Thorough Validation Environment Broadcom
System Verification: Formal Verification Formal Verification for Analog/Mixed Signal Designs Texas Instruments
PCB and IC Packaging Design IBIS Plus Model Generation and Validation Using Sigrity-T2B for High-Speed IO Interface Qualcomm

Speaking about the conference, Jaswinder Ahuja, corporate vice president and managing director of Cadence India, said, “CDNLive India has grown to become one of the most popular and eagerly awaited conferences in the Indian electronics ecosystem, attracting attendees in the thousands. The increase in attendee numbers over the years is a testament to the growing semiconductor and electronics design community in India. Each year, we look forward to having our customers share their latest successes with our technology through their session presentations, and we’d like to thank all of our presenters and congratulate our 2017 award winners. CDNLive India has proven to be a great platform to drive innovation in the face of emerging design complexities.”

The two-day conference, held on September 7 and 8, provided an opportunity for participants to network with peers and industry leaders, share best practices, understand the latest solutions and discover new techniques to address their most difficult design challenges. The conference featured over 85 user presentations, four keynotes, an exhibition area, and Cadence demo pods.


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